Positron AI has raised $875 million in a combined Series C and Series C-1 round, valuing the Reno-based startup at $5 billion post-money. The financing, co-led by NEA, Andra Capital, Atreides Management, Valor Equity Partners, and SemiAnalysis Capital, represents a roughly five-fold markup from the company’s February 2026 Series B valuation of just over $1 billion. The speed and scale of the markup reflect a specific institutional bet: that the economics of AI inference can be fundamentally redesigned by replacing expensive, supply-constrained high-bandwidth memory with commodity LPDDR5X.
The Asimov chip, Positron’s custom inference ASIC built on TSMC’s N3P process, is the mechanism behind this bet. Where NVIDIA’s HBM-based GPUs are designed around peak bandwidth, Asimov is designed around memory capacity and utilization efficiency. A single chip delivers 288 GB of on-package LPDDR5X, expandable to 2.3 TB via CXL expansion. For context, NVIDIA’s H100 offers 80 GB of HBM3, the H200 offers 141 GB of HBM3e, and even the upcoming Rubin architecture provides 288 GB of HBM4. Positron’s memory advantage ranges from roughly 2x to 29x depending on which NVIDIA part is the comparison target.
The technical claim that makes this plausible is bandwidth utilization. NVIDIA GPUs typically realize less than 30% of their theoretical memory bandwidth on transformer inference workloads, a consequence of the mismatch between HBM’s optimized sequential access patterns and the random-access patterns that define inference. Positron claims Asimov achieves greater than 90% utilization on the same workloads, effectively closing the gap between peak and realized bandwidth. At 2.76 TB/s of realizable bandwidth against the H100’s 3.35 TB/s theoretical peak-of which less than 1 TB/s is typically achieved in practice-the Asimov’s effective throughput becomes competitive despite using cheaper memory technology.
The strategic implications extend beyond benchmark comparisons. HBM is the chokepoint of the current AI supply chain. It requires advanced CoWoS packaging, consumes scarce SK hynix and Samsung production capacity, and carries a significant cost premium. By designing around LPDDR5X-a commodity memory technology available from multiple suppliers-Positron is attempting to bypass the HBM bottleneck entirely. The Asimov chip uses an organic substrate rather than CoWoS, air-cooling rather than liquid, and standard PCIe Gen6 interfaces with CXL expansion. This is not a chip designed for the hyperscale data center. It is designed for brownfield deployment: existing facilities that cannot support the thermal and power requirements of liquid-cooled GPU clusters.
The pricing dynamics of the broader AI inference market amplify the appeal of this approach. As frontier labs compress token costs-the Silicon Data LLM Token Expenditure Index dropped below $1 per million tokens for the first time in early September-the cost structure of the underlying silicon becomes the primary margin determinant. A chip that delivers comparable inference performance at lower power consumption (400W versus 700W for H100) and lower memory cost creates structural margin advantage for operators running high-volume, long-running agentic workloads.
This challenge to NVIDIA’s HBM-centric model arrives at a moment when the compute landlord thesis is being reshaped from multiple directions. OpenAI’s Jalapeno chip demonstrated that AI labs can design their own silicon. DeepSeek’s V4.1 Flash CED architecture proved that architectural innovation can reduce inference costs by 80% without new hardware. Positron’s Asimov adds a third vector: commodity memory as a viable foundation for frontier inference. Each approach attacks a different layer of the same problem-the cost and supply constraints that make NVIDIA’s HBM stack the dominant-and most expensive-path to inference at scale.
The investor lineup signals that this is not a speculative bet on unproven technology. NEA, Atreides Management, and Valor Equity Partners are all return investors from earlier rounds, providing continuity of conviction. Jim Clark, the co-founder of Silicon Graphics and Netscape, is leading the Series C-1 tranche-a founder whose career has been defined by building the computational infrastructure that others build upon. SemiAnalysis Capital, the investment arm of Dylan Patel’s semiconductor analysis firm, brings deep domain expertise in chip architecture and supply chain dynamics. The inclusion of the Qatar Investment Authority signals sovereign interest in inference infrastructure outside the NVIDIA-HBM axis.
The execution timeline, however, introduces significant risk. Asimov is scheduled for tapeout by the end of 2026, with production slated for the second half of 2027. This means the chip will not be commercially available for at least twelve months-a period during which NVIDIA will ship Rubin, AMD will expand its MI400 line, and multiple other inference-focused startups will bring competing designs to market. The Titan system, which pairs four to eight Asimov chips per node and targets models larger than 16 trillion parameters with context windows exceeding 10 million tokens, remains a specification sheet rather than a validated product.
For investors and policy watchers, the Positron round represents something more significant than a single startup’s fundraising milestone. It is evidence that capital is flowing toward inference infrastructure alternatives that challenge the HBM supply chain’s structural dominance. If Asimov delivers on its utilization claims, the compute landlord thesis must account for a new variable: the possibility that the most expensive component in the inference stack-the memory subsystem-can be replaced with commodity hardware without sacrificing performance. The question is not whether LPDDR5X can match HBM’s peak bandwidth. It cannot. The question is whether 90% utilization of cheap memory beats 30% utilization of expensive memory. Positron just raised $875 million on the bet that it does.